| PART |
Description |
Maker |
| HCF4013 HCF4013M013TR HCF4013B HCF4013BEY HCF4013B |
4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
DUAL 'D' - TYPE FLIP-FLOP
DUAL D-TYPE FLIP FLOP
|
STMICROELECTRONICS[STMicroelectronics]
|
| MC100ELT23 MC100EL12DTR2 MC10H131FNR2 MC100H640FNR |
5V Dual Differential PECL to TTL Translator
5V ECL Low Impedance Driver
Dual Type D Master-Slave Flip-Flop
ECL/TTL Clock Driver
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
3.3V / 5V ECL ÷4 Divider
Quad 2-Input NOR Gate
3.3V ECL Dual Differential Data and Clock D-Type Flip-Flop with Set and Reset
3.3V / 5V Hex Differential Line Receiver / Driver
3.3V / 5V Triple ECL Input to LVPECL/PECL Output Translator
|
ON Semiconductor
|
| 74HC_HCT74 |
Dual D-type flip-flop with set and
|
Philips
|
| 74LV74D-Q100 74LV74PW-Q100 |
Dual D-type flip-flop with set and reset; positive-edge trigger
|
NXP Semiconductors
|
| 74HC74N652 |
Dual D-type flip-flop with set and reset; positive edge-trigger
|
NXP Semiconductors
|
| MC74VHCT74A06 MC74VHCU04DR2G MC74VHCU04DR2 MC74VHC |
Hex Inverter (Unbuffered)
Dual D?Type Flip?Flop with Set and Reset
|
ONSEMI[ON Semiconductor]
|
| 74HC74DR2 74HC74DR2G 74HC74D 74HC74 74HC74DTR2G 74 |
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
Dual D Flip-Flop with Set and Reset(带设置和复位的双D触发 双D触发器的设置和复位（带设置和复位的双触发器）
|
ONSEMI[ON Semiconductor]
|
| 74F50729 N74F50729N I74F50729D I74F50729N N74F5072 |
Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| MC74LVX74 MC74LVX74DT ON1600 MC74LVX74D MC74LVX74M |
From old datasheet system
LOW-VOLTAGE CMOS
DUAL D-TYPE FLIP-FLOP WITH SET AND CLEAR WITH 5V-TOLERANT INPUTS
|
MOTOROLA[Motorola, Inc]
ONSEMI[ON Semiconductor]
|
| 5962F9863201VCC 5962F9863201V9A 5962F9863201VXC AC |
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
Radiation Hardened Dual J-K Flip-Flop with Set and Reset 辐射硬化的设置和复位JK触发
|
Intersil Corporation
Intersil, Corp.
|
| 74HC74DR2 74HC74DG |
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
|
ON Semiconductor
|
